Metal-insulator-metal (MIM) capacitor structure and methods of fabricating same

ABSTRACT

A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode. Furthermore, a multi-rate etching process may be used to etch the top electrode and insulator layer of an MIM structure, using a first, higher rate to perform an anisotropic etch up to a point proximate an interface between the conductive and dielectric materials respectively defining the top electrode and insulator layer of the MIM structure, and then using a second, lower rate to perform an anisotropic etch to a point proximate an etch stop layer defined on the bottom electrode of the MIM structure.

FIELD OF THE INVENTION

[0001] The invention is generally related to integrated circuitfabrication, and more particularly, to the fabrication ofmetal-insulator-metal (MIM) capacitor structures in integrated circuits.

BACKGROUND OF THE INVENTION

[0002] Reduced circuit area is an economic driver of themicroelectronics revolution. Integrated circuits, or chips, continue toincrease in circuit density due to reduced sizes of circuit componentsmade possible through the implementation of smaller and smaller circuitdesign rules. As more and more components are designed into anintegrated circuit, the complexity of the integrated circuit isincreased, thereby enabling greater functionality in the circuit.Moreover, functions that were once performed by multiple integratedcircuits can often be integrated together onto the same integratedcircuit, thereby reducing costs, power consumption, and size, whileimproving speed and interconnectivity.

[0003] In addition, other components such as capacitors, inductors,resistors, and other types of passive components are increasinglyintegrated into integrated circuits, thereby eliminating the need toincorporate separate, discrete components in a circuit design thatotherwise increase circuit size, power consumption and cost. Both thedemands of smaller circuit design rules, and the desire to incorporatevarious passive circuit components in an integrated circuit, however,has demanded new materials, new structures and new processing techniquesto be incorporated into the integrated circuit fabrication process.

[0004] One type of passive component that is increasingly incorporatedinto many integrated circuit designs is a metal-insulator-metal (MIM)capacitor, which typically incorporates a stacked arrangement ofmaterials that includes, in the least, top and bottom conductiveelectrodes incorporating a conductive material, and an intermediateinsulator layer incorporating a dielectric material. Typically, a MIMcapacitor is fabricated between the outermost metal layers in anintegrated circuit (e.g., between the M5 and M6 layers), which orientsthe capacitor relatively far from the underlying semiconductorsubstrate, such that parasitic capacitance effects with the substrateare minimized.

[0005] MIM capacitors are often utilized, for example, in high frequency(e.g., RF) telecommunications applications such as in cell phones andother wireless devices, as well as other telecommunications products.Often, MIM capacitors are used to provide various functions in anintegrated circuit, e.g., decoupling with a power supply, analogfunctions such as analog-to-digital conversions and filtering, andtermination of transmission lines. Decoupling applications generallyhave relatively loose leakage current requirements, whereas analogapplications, such as analog-to-digital converters (ADC's), typicallyrequire closer capacitor matching and relatively good voltage linearity.Moreover, in many telecommunications applications, particularly inhandheld applications, low loss and relatively small temperaturelinearity are desired.

[0006] Given the ever-present desire to reduce the sizes of componentsin an integrated circuit, it is desirable to minimize the circuit areaoccupied by MIM capacitors. To provide a desired capacitance from a MIMcapacitor within a smaller circuit area, therefore, an increase in thecapacitance density of the capacitor (which based upon present designrules is typically expressed in terms of femtofarads per squaremicrometer (fF/μm²)) is required.

[0007] Conventional approaches to increasing MIM capacitor capacitancedensity have typically focused upon using high dielectric constant (K)dielectric materials in the insulator layer of a MIM capacitor,decreasing insulator layer thickness and/or utilizing structuregeometries that increase perimeter (which increases fringe and lateralcapacitance effects).

[0008] For example, high dielectric constant materials such as tantalumpentoxide, tantalum oxynitride, silicon nitride, barium strontiumtitanate (BST), lead zirconium titanate, and hafnium oxide have beenused in some conventional MIM capacitor designs. Furthermore, variousprocess improvements have been utilized to deposit such materials withreduced thicknesses, and without inducing short circuits between theelectrodes of the capacitor design.

[0009] In addition, some MIM capacitor designs have relied upon multiple“fingers” forming one of the electrodes of a design. The multiplefingers extend generally parallel one another and incorporate anincreased perimeter compared to a single contiguous electrode occupyingthe same circuit area.

[0010] Nonetheless, despite the improvements made in conventional MIMcapacitor designs, many such designs are limited to at most about 1fF/μm². At this density, however, capacitors providing the necessarycapacitance for many applications (e.g., many RF applications) areinordinately large, particularly for more advanced design rules. As anexample, at 1 fF/μm², a 100 nF capacitor would require a circuit area ofapproximately 1 cm per side, which, when used in connection withtechnology such as a 0.25 μm RF BiCMOS technology, results in a widththat is approximately 40,000 times the minimum feature size for theintegrated circuit.

[0011] Therefore, a significant need continues to exist in the art for amanner of improving the capacitance density in a MIM capacitorstructure.

[0012] Another difficulty experienced in connection with MIM capacitorfabrication is oxidation of the bottom electrode during fabrication.Particularly when electrode materials such as titanium nitride (TiN) areused, oxidation of the electrode prior to deposition of the insulatorlayer can occur and form titanium oxides that cause current leakage.Prior attempts to inhibit oxidation include, for example, depositing theinsulator layer in the same tool in which the electrode material isdeposited. However, by depositing both layers in the same tool,patterning and etching of both layers must generally occur together,requiring the insulator layer to have the same layout as the bottomelectrode. Furthermore, close coupling of the bottom electrode anddielectric film depositions does not guarantee a clean interface betweenthe materials.

[0013] Therefore, a significant need also exists in the art for a mannerof inhibiting the formation of oxidation on a bottom electrode of a MIMcapacitor structure.

[0014] Yet another difficulty experienced in connection with MIMcapacitor fabrication is that of patterning and etching the MIMcapacitor structure in connection with aluminum-based circuitinterconnects. In particular, whenever aluminum or aluminum alloyinterconnects, as are commonly used in the metal layers of an integratedcircuit, are exposed to etching chemistry such as CCl₄, BCl₃, Cl₂, etc.,aluminum chloride is often generated as a byproduct thereof,necessitating the use of an additional aluminum polymer removal step toclean the partially-fabricated integrated circuit. Adding such a stepincreases processing time and expense, and may not remove all chlorine(Cl) containing compounds that can cause Al corrosion.

[0015] Therefore, a significant need also exists in the art for a mannerof etching a MIM capacitor structure without undue exposure of aluminuminterconnects to chlorine chemistry.

SUMMARY OF THE INVENTION

[0016] The invention addresses these and other problems associated withthe prior art by providing in one aspect a Metal-Insulator-Metal (MIM)capacitor structure and method of fabricating the same in an integratedcircuit in which a sidewall spacer extends along a channel definedbetween a pair of legs that define portions of the MIM capacitorstructure. Each of the legs includes top and bottom electrodes and aninsulator layer interposed therebetween, as well as a sidewall thatfaces the channel. The sidewall spacer incorporates a conductive layerand an insulator layer interposed between the conductive layer and thesidewall of one of the legs, and the conductive layer of the sidewallspacer is physically separated from the top electrode of the MIMcapacitor structure. By orienting a sidewall spacer, with a conductivelayer that is physically separated from a top electrode, along thechannel, it has been found that lateral capacitance effects between thepair of legs that face the channel are substantially increased,resulting in substantial improvements in overall capacitance density forthe MIM capacitor structure.

[0017] While other manners of fabricating a sidewall spacer may be usedconsistent with the invention, one suitable manner includes formingfirst and second bottom electrodes that extend generally parallel to oneanother and defining a channel therebetween, depositing an insulatorlayer over the first and second bottom electrodes and in the channel,depositing a conductive layer over the insulator layer, and etching thedeposited conductive and insulator layers. Etching these layers resultsin the definition of first and second top electrodes that oppose thefirst and second bottom electrodes, as well as a physical separationbetween a portion of the conductive layer in the channel and the firstand second top electrodes.

[0018] The invention also addresses in another aspect a number ofimprovements to the process of making MIM capacitor structures. Forexample, one aspect of the invention addresses the difficultiesassociated with oxidation of the bottom electrode of a MIM capacitorstructure by providing a MIM capacitor structure and method offabricating the same in an integrated circuit in which a surface of thebottom electrode is ammonia plasma treated. As another example, anotheraspect of the invention addresses the difficulties associated with theexposure of aluminum interconnects to etching chemistry, by utilizing amulti-rate etching process to etch the top electrode and insulator layerof an MIM structure, using a first, higher rate to perform ananisotropic etch up to a point proximate an interface between theconductive and dielectric materials respectively defining the topelectrode and insulator layer of the MIM structure, and then using asecond, lower rate to perform an anisotropic etch to a point proximatean etch stop layer defined on the bottom electrode of the MIM structure.Through the use of an etch stop layer, underlying aluminum interconnectsare protected from undue exposure to etching chemistry, thus eliminatingin many instances the need for the aluminum polymer removal and relatedcleaning processes.

[0019] These and other advantages and features, which characterize theinvention, are set forth in the claims annexed hereto and forming afurther part hereof. However, for a better understanding of theinvention, and of the advantages and objectives attained through itsuse, reference should be made to the Drawings, and to the accompanyingdescriptive matter, in which there is described exemplary embodiments ofthe invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1 is a schematic top plan view of an integrated circuitincorporating an exemplary Metal-Insulator-Metal (MIM) capacitorstructure consistent with the invention.

[0021]FIG. 2 is an isometric cross-sectional view of the MIM capacitorstructure of FIG. 1, taken through lines 2-2 thereof, and with the vias.

[0022]FIG. 3 is an enlarged cross-sectional view of two legs in the MIMcapacitor structure of FIG. 2, illustrating the capacitance componentstherefor.

[0023]FIG. 4 is a schematic top plan view of an alternate MIM capacitorstructure layout to that of FIG. 1.

[0024]FIG. 5 is a flowchart illustrating a process for fabricating theintegrated circuit of FIG. 1.

[0025] FIGS. 6A-6G are schematic cross-sectional views illustratingfabrication of a MIM capacitor structure using the process of FIG. 5.

[0026]FIG. 7 is a flowchart illustrating a process for implementing theinsulator and TiN layer etching step referenced in FIG. 5.

[0027]FIG. 8 is a graph illustrating silicon nitride growth on testwafers as a result of ammonia plasma treatment.

[0028]FIG. 9 is a graph illustrating capacitance density of test wafers,contrasting the capacitance densities obtained using 1 μm and 2 μm M5layer thicknesses.

[0029] FIGS. 10-13 are schematic top plan views of additional alternateMIM capacitor structure layouts to that of FIG. 1.

DETAILED DESCRIPTION

[0030] The embodiments of the invention described hereinafter utilizeseveral structural and process improvements to improve the capacitancedensity of a Metal-Insulator-Metal (MIM) capacitor structure in afabricated integrated circuit. These structural and process improvementsare generally compatible with conventional integrated circuitfabrication processes, dimensions and process equipment, thus providingimproved MIM capacitor performance with minimal additional manufacturingsteps and/or costs. For example, it is believed that the inventionpermits MIM capacitor structures having picofarad-range capacitances tobe incorporated into otherwise standard integrated circuits andfabrication processes.

[0031] From a structural standpoint, the combination of a highdielectric constant material used for the insulator layer of the MIMcapacitor structure, and a layout that attempts to maximize theperimeter-to-area ratio of the structure (and thus maximize fringecapacitance effects), provides substantially improved capacitancedensity over many conventional MIM structures. Moreover, the layout isfurther configured to provide recessed channels that run betweenopposing legs of the structure, so that one or more sidewall spacers,having conductive material that is physically separated from the topelectrode of the MIM structure by a high K dielectric constant material,can be formed within the channels to further improve lateral capacitanceeffects, and thus further improve the capacitance density of the MIMstructure.

[0032] From a process standpoint, ammonia plasma treatment may beutilized on the bottom electrode of a MIM structure to improve thebarrier characteristic of the surface of the bottom electrode to oxygen,thereby inhibiting oxidation of the bottom electrode prior to depositionof the insulator layer. Moreover, a multi-rate etching process may beutilized to etch the top electrode and insulator layer of an MIMstructure, using a first, higher rate to perform an anisotropic etch upto a point proximate an interface between the conductive and dielectricmaterials respectively defining the top electrode and insulator layer ofthe MIM structure, and then using a second, lower rate to perform ananisotropic etch to a point proximate an etch stop layer defined on thebottom electrode of the MIM structure.

[0033] Turning to the drawings, wherein like numbers denote like partsthroughout the several views, FIG. 1 illustrates an integrated circuit10 incorporating a MIM capacitor structure 12 consistent with theprinciples of the invention. Structure 12 is implemented using aserpentine layout that incorporates a plurality of leg portions or legs14 laid out in a generally parallel relationship to one another, andcoupled together by bridge portions 16 proximate the ends of each pairof legs. Each pair of adjacent legs 14 defines a recessed channel 18therebetween. Moreover, an array of vias 20 are disposed over much ofthe surface area of the structure to provide interconnection with anupper interconnect layer (not shown in FIG. 1), e.g., the M6 layer whenthe capacitor structure is formed between the M5 and M6 layers of anintegrated circuit. It will be appreciated that various via layouts,spacings and geometries, as well as other inter-layer interconnects, maybe utilized to interconnect the MIM capacitor structure with aconductive layer (e.g., any of the interconnect layers Mx) in integratedcircuit 12.

[0034] Turning next to FIG. 2, the basic capacitive structure of eachleg 14 in MIM capacitor structure 12 is illustrated in greater detail.In particular, each leg 14 includes a bottom electrode 30 formedprimarily of a block of conductive material 32 such as aluminum, copperor an alloy thereof, and coated with a conductive layer 34 thatfunctions in the illustrated embodiment as both an anti-reflectioncoating (ARC) and an etch stop layer for subsequent etching processes.

[0035] In the illustrated embodiment, for example, the MIM capacitorstructure is described as being formed between the M5 and M6 layers in asix metal layer integrated circuit, whereby conductive material 32 isdeposited and patterned during deposition and patterning of the M5 layerin the circuit. By orienting the structure in the outermost layers ofthe circuit, parasitic capacitance effects with the substrate areminimized, and the quality factor of the capacitor is improved.Moreover, by using a low K dielectric beneath the MIM capacitorstructure, substrate parasitic effects are further reduced. However, itwill be appreciated that a MIM capacitor structure consistent with theinvention may be fabricated within and between various otherinterconnect layers within an integrated circuit consistent with theinvention.

[0036] Layered over bottom electrode 30 is an insulator layer 36, formedof a dielectric material such as tantalum pentoxide (Ta₂O₅). Layeredover insulator layer 36 is a conductive layer 38 forming the topelectrode for the MIM capacitor structure. As will be discussed below,insulator layer 36 and top electrode 38 may be cooperatively patternedduring an etching process, and as a result, typically these two layerswill have the same geometric proportions in many implementations.

[0037] As also shown in FIG. 2, each leg 14 of MIM capacitor structure12 that runs adjacent another leg 14 and forms a channel 18 therebetweenhas a sidewall 40 that faces the channel. Given the typical thickness ofthe M5 layer as compared to each of layers 34, 36 and 38, nearly all ofthe sidewall 40 is defined along layer 32, and the height of thesidewall is principally controlled by the thickness of the M5 layer.

[0038] Also positioned within each channel 18 are one or more sidewallspacers 42 that extend generally parallel to the sidewalls 40 of thelegs 14 in structure 12. Each sidewall spacer 42 includes a conductivelayer 44 and an insulator layer 46 interposed between layer 44 andsidewall 40 of an adjacent leg 14. As will become more apparent below,conductive layer 44 is typically deposited concurrently with conductivelayer 38, and insulator layer 46 is deposited concurrently withinsulator layer 36, with generally the same thicknesses. Other mannersof forming the sidewall spacers may be used in the alternative, e.g.,separate using deposition steps, technologies, and/or materials than areused for layers 36 and 38.

[0039] Conductive layer 44 in each sidewall spacer 46 is physicallyseparated from the top electrode of the MIM capacitor structure, i.e.,there is no direct conductive path between the two components. The onlyelectrical coupling between the components is via capacitive effects. Inthe illustrated embodiment, there is a physical separation between layer44 and bottom electrode 30 (and hence, between layer 44 and the M5layer), although in other embodiments a direct conductive path may beprovided between these components.

[0040] Typically a sidewall spacer is provided alongside each sidewallfacing a channel defined between adjacent legs in a MIM capacitorstructure, although only one sidewall spacer may be used in someembodiments. Furthermore, each sidewall spacer typically runs along theentire length of each channel, although embodiments may be envisionedwhere sidewall spacers are only provided along a portion of a givenchannel, as well as only in a portion of all channels, defined in a MIMcapacitor structure.

[0041] Each sidewall spacer functions to increase both the fringe andlateral components of capacitance for the MIM capacitor structure, byincreasing the dielectric constant of the material between the legs ofthe serpentine. Moreover, as will be discussed in greater detail below,it has been found that capacitance density increases as the sidewall(and hence, the sidewall spacer) height is likewise increased.

[0042] It is believed that, with the necessary limitations on theminimum separations between legs, the lateral components of capacitanceare predominantly affected by the presence of the sidewall spacers.Accordingly, it is further believed that increases in capacitance viathe sidewall spacers are predominantly realized through increasing thedielectric constant between the legs, which is obtained by increasingthe dielectric constant of the deposited material, and increasing theheight of the sidewalls (and thus the height of the spacers). It is alsobelieved that, in some embodiments, sidewall spacers may not require anyconductive material, such that, with the herein-described process, aseparate etching step could be used to remove the conductive materialused in the sidewall spacers. For other processes, the sidewall spacersmay be formed separately from the deposition and etching steps that formthe insulator layer and top electrode for the MIM capacitor structure,and as such, various techniques could be used to inhibit the depositionof conductive material for the sidewall spacers during deposition of thetop electrode material.

[0043] As shown in FIG. 3, for example, the principal componentsaffecting the capacitance density of the herein-described MIM capacitorstructures are areal capacitance, fringe capacitance, and lateralcapacitance, denoted respectively by the labels A, F and L. Arealcapacitance is principally affected by the dielectric constant, area andthickness of the insulator layer, while fringe capacitance isprincipally affected by the perimeter of the layout. Lateral capacitanceis based upon the capacitive coupling between adjacent legs in thelayout, and it is believed that the incorporation of sidewall spacersenhances both the fringe and lateral capacitive components for a MIMcapacitor structure.

[0044] In the illustrated embodiment of FIGS. 1-3, where a 0.25 μmBiCMOS technology is used, the insulator layer and the TiN top electrodehave minimum dimensions of about 5 μm spacing and about 2 μm width ineach leg, while the bottom electrode is slightly oversized relative tothe top electrode and insulator layer, e.g., the MIM top electrode isabout 1 ∞m inbound from the edge of the M5 bottom electrode, withminimum dimensions of about 3 μm spacing and about 4 μm width in eachleg, thereby defining channels of about 3 μm in width between adjacentlegs. The vias interconnecting the MIM capacitor structure to the nextmetal layer (e.g. M6) may have a pitch of about 4 μm and a diameter ofabout 2 μm when formed from hot aluminum, and a pitch of about 3 μm anda diameter of about 1 μm when formed from tungsten. Larger dimensionsmay be used, although typically the perimeter-to-area ratio of theresulting structure will decrease, and result in less lateral and fringecomponents to the overall capacitance of the structure.

[0045] Also, in the illustrated embodiment described above, theinsulator layer is formed of a high K dielectric such as siliconnitride, titanium dioxide, tantalum pentoxide, barium strontium titanate(BST), lead zirconium titanate, hafnium oxide, tantalum oxynitride,etc., having a thickness of as little as about 80 angstroms, which isoften limited by the defectivity of the layer itself and the underlyinglayers. A thickness of about 400-500 angstroms has been found to give acapacitance density of about 5 fF/μm², while thinner layers providecomparatively greater capacitance density. While thicker insulatorlayers may be used, often the capacitance density is lowered belowdesirable levels. In the implementation discussed hereinafter, atantalum pentoxide (Ta₂O₅) insulator layer is used, although other highK dielectrics, as well as lower K dielectrics, may be used in otherimplementations.

[0046] The top electrode may be formed of about 3000 angstroms of TiN,but is typically limited only by the overetch of the V5 dielectric etch.For example, if the selectivity of the oxide etch is such that about 750angstroms of TiN is consumed, then an about 1500 to about 2000 angstromTiN top electrode thickness will typically be sufficient in manyapplications. By using a 3000 angstrom thickness, the Al—Cu or Ti/TiNliner (in the case of W plugs) may be kept a sufficient distance fromthe top electrode/insulator layer interface, and thereby minimize thepossibility of reaction between these layers at an elevated temperature.

[0047] The bottom electrode may be formed of a TiN anti-reflectivecoating (ARC) layer deposited on the M5 layer (typically formed ofaluminum, copper, or an alloy thereof, depending upon the IC fabricationtechnology used). Typically, the thickness of the TiN layer is set bythe patterning requirements of the M5 layer; however, a minimum of about250 to 300 angstroms is typically desired to reduce or eliminatereflections during the subsequent patterning process, which otherwisemight cause notches to form in the photoresist material. Thicker TiNlayers may be used, however, and may have advantages in the throughputof the multi-rate etch process described in greater detail below. Forthe M5 portion of the bottom electrode, a thickness of about 1 μm toabout 4 μmay be used, although thinner layers, e.g., about 5000-7000angstroms may be used as well. As will become more apparent below, byincreasing the M5 layer thickness, the fringe component of thecapacitance is typically increased. However, the maximum thickness willtypically depend upon the ability of the film deposition tool to fillhigh aspect ratio features such as the channels between the bottomelectrode portions in adjacent legs of the MIM capacitor structure. Forexample, many such tools are limited to a height-to-width ratio of about3.5:1.

[0048] Other materials may be utilized in the top and bottom electrodes,e.g., various metals and silicides of tungsten (W), titanium (Ti),tantalum (Ta), manganese (Mn), molybdenum (Mo), etc. In addition, amaterial such as ruthenium may be used as a barrier layer over TiN toprevent oxidation of the TiN layer.

[0049] It will be appreciated that, depending upon the capabilities ofvarious fabrication technologies that may be utilized in the fabricationof integrated circuits, the dimensions, thicknesses, and materialsutilized in an MIM capacitor structure may vary in otherimplementations. Therefore, the invention is not limited to theparticular dimensions, thicknesses, and materials described herein.Moreover, it will be appreciated that the relatively layer thicknessesand dimensions shown in the figures are not necessarily true to scale,as the relative thicknesses of some layers (e.g., the TiN layers and theinsulator layers, which are often several orders of magnitude thinnerthan the M5 layer) have been exaggerated to facilitate a betterunderstanding of the overall structure of a MIM capacitor consistentwith the invention. Therefore, the invention is not limited by theparticular thicknesses illustrated in the figures.

[0050] Returning to FIG. 1, any number of legs and lengths of legs maybe used in a serpentine capacitor layout consistent with the invention.Moreover, it will be appreciated that a wide variety of alternatecapacitor layouts may be utilized in the alternative, in particular,various layouts that maximize the perimeter-to-area ratio of astructure. As one example, FIG. 4 illustrates a MIM capacitor structure12′ incorporating a “negative serpentine” layout, where a channel 50,rather than the capacitive structure 52, forms a serpentine design. Withthe negative serpentine layout, the capacitive structure 52 is definedby an interleaved comb pattern, where legs 54 alternately extend inwardfrom a pair of opposing rails 56.

[0051] In addition, it should be appreciated that patterns can becombined. As an example, FIG. 10 illustrates an exemplary layout 12″which is in many respects similar to the combination of layouts 12 and12′, where a positive serpentine pattern 13A is essentially embeddedwithin the channel defined in an interleaved comb, or negativeserpentine, pattern 13B, such that the positive and negative serpentinepatterns are interleaved with one another. Given the ability to use viaconnections to other layers (e.g., M6), FIG. 10 also illustrates thatthe electrodes of a capacitor structure need not necessarily becontiguous throughout the electrode layers.

[0052] Many other suitable designs utilizing high perimeter-to-arearatios will be appreciated by one of ordinary skill in the art havingthe benefit of the instant disclosure, e.g., various tiled serpentineand/or comb patterns, spiral patterns, and combinations thereof. As anexample, FIGS. 11-13 illustrate several exemplary layouts 12′″, 12″″ and12″″′, also suitable for incorporation into a MIM capacitor structureconsistent with the invention. Both positive and negative layouts basedupon these patterns may be suitable for use, as may various combinationsof the repeating elements in these patterns.

[0053] Now turning to FIG. 5, an exemplary process for fabricating anintegrated circuit that incorporates a MIM capacitor structureconsistent with the invention is illustrated at 60, and begins at block62 by performing conventional fabrication processing up to the point ofM5 deposition, e.g., using a 0.25 μm BiCMOS process technology. Next, asshown in blocks 64 and 66, the conductive material for the M5 layer,e.g., an aluminum-copper alloy such 0.5% by weight of copper in abalance of aluminum, is deposited on the integrated circuit, followed bydeposition of a thin (e.g., about 300 angstrom) coating of titaniumnitride (TiN), e.g., via reactive physical vapor deposition (PVD),otherwise known as sputtering. The Al—Cu deposition process desirablyuses a lower deposition temperature (e.g., about 200° C.) to produce asmooth fine grained material. It has been found that high temperaturesduring sputtering can cause the incorporation of contaminants in thegrowing film, which can lead to the formation of surface protrusionsknown as hillocks. The capacitor dielectric can often break down atthese protrusions due to high electric field intensity, thereby causinga short circuit.

[0054] As discussed above, the thickness of the M5 stack (thealuminum-copper and TiN layers) directly affects the lateral capacitanceeffects between adjacent legs of the design, and as such, a relativelythick M5 layer, e.g., 2 μm or more, may be desirable in manyembodiments.

[0055] Next, as illustrated in block 68, an ammonia plasma treatmentstep is performed to treat the exposed surface of the TiN layer toreduce or eliminate oxidation of the surface prior to and duringdeposition of the insulation layer of the capacitor. In particular, ithas been found that performing an ammonia plasma treatment serves tobombard the surface of the TiN layer with nitrogen ions to “stuff” thecolumnar grain boundaries in the TiN structure and thereby reduce theformation of titanium oxide (TiO) on the surface of the TiN layer.

[0056] In the illustrated embodiment, a multi-station plasma enhancedchemical vapor deposition (PECVD) tool may be used to generate anammonia plasma. The process may use a silicon nitride process as astarting point, by removing the silane flow and using a total RF power(about 13.56 MHz) of about 0.1 to 1 Watts/cm², with up to about 50% lowfrequency RF (about 230 kHz) power. The plasma anneal may include anammonia (NH₃)/inert gas (e.g., N₂ or Ar) mixture in a plasma discharge,and in an atmosphere at about 10 mTorr to 10 Torr pressure. Theflowrates of the ammonia and inert gas are typically set to the levelsthat achieve the best uniform growth of silicon nitride on a silicontest wafer substrate. The wafer temperature during the treatment may beheld at a level of about 300-500° C., which is compatible with aluminumprocessing, and the treatment time may be approximately the same as thatrequired to form a silicon nitride film of less than 100 angstroms on asilicon substrate.

[0057] Turning briefly to FIG. 6A, an exemplary integrated circuit 100is shown subsequent to the processes performed in blocks 62-66 of FIG.5. At 102 is illustrated the semiconductor substrate, including all ofthe integrated circuit components up to the M5 layer. An aluminum-copperlayer deposited in block 64 is represented at 104, and an ammonia plasmatreated TiN layer, deposited in block 66, and ammonia plasma treated inblock 68, is represented at 106.

[0058] Returning to FIG. 5, after ammonia plasma treatment, the M5 stackis patterned by conventional lithography and etch techniques to form thebottom electrode for the MIM capacitor structure (block 70). Asdiscussed above, the presence of the TiN layer serves as ananti-reflective coating that minimizes reflections of the exposure lightthat could otherwise cause overexposure of areas of the photoresistpattern and result in loss of pattern transfer fidelity such as due tounintended notching of photoresist lines. The resulting patternedstructure is illustrated in FIG. 6B. For illustrative purposes, FIG. 6Billustrates the patterning of the M5 stack into a bottom electrode 108and an M5 bonding pad 110.

[0059] Next, in block 72 (FIG. 5) an annealing step is performed toanneal the M5 and TiN layers in a reducing atmosphere to relive stressin the metal layer. For example, a heat treatment at about 420° C. forabout 30 minutes may be used to promote intermetallic formation anddeformation of the M5 metal prior to dielectric deposition. It isbelieved that the temperature at which subsequent dielectric depositionis performed is high enough to cause aluminum grain growth, and thus, byperforming a pre-deposition anneal process, film deformation and graingrowth is promoted prior to deposition, resulting in a higher qualitysurface upon which to deposit the dielectric. Cracks and other surfacedeformations in the resulting dielectric layer are typically avoided asa result of the annealing process.

[0060] Next, in block 74 (FIG. 5) a high dielectric constant film (e.g.,tantalum pentoxide in the illustrated implementation) is deposited asthe capacitor insulator layer, typically with a thickness of less thanabout 50 nm, e.g., with a thickness of about 40 nm. Various depositiontechnologies may be used, including both physical and chemical vapordeposition, typically depending upon the type of dielectric materialbeing deposited. For tantalum pentoxide, for example, a Metal OrganicChemical Vapor Deposition (MOCVD) process may be used, e.g., using aEureka 2000 MOCVD cluster tool available from Jusung EngineeringCompany, Ltd., which incorporates a gas boundary layer in the reactor toimprove film uniformity, and which includes multiple modules capable ofperforming both the deposition process and a post-deposition plasmaanneal. Incoming gases may be pre-heated to maintain process temperaturestability.

[0061] Various deposition control parameters may be used. For example,deposition of tantalum pentoxide may be performed at about 430° C. usingtantalum pentaethoxide [TAETO, Ta(OCH₂CH₃)₅] and oxygen, with the TAETOsupplied to the reactor by a single or multiple vaporizer deliverysystem at about 40 mg/min for each vaporizer, with an oxygen flow rateof about 10 sccm or higher and at about, 0.4 Torr up to about 10 Torr.

[0062] Next, in block 76 (FIG. 5), and within the same MOCVD tool, thedielectric layer is plasma annealed, e.g,. using an oxygen annealperformed at about 430° C. with about 200 sccm of oxygen at about 0.4Torr or higher, for about 60 seconds at about 300 Watts RF power. Doingso typically reduces the dielectric carbon content and more fullyoxidizes the dielectric layer. In some embodiments, annealing may not berequired, while in others, other anneal processes, using other processparameters, may be used in the alternative.

[0063] As shown in FIG. 6C, the deposition and annealing performed inblocks 74 and 76 (FIG. 5) result in the deposition of a dielectric layer112, oriented both on top of the TiN layer 106 and on sidewalls 114 ofthe patterned M5 stack features, as well as on top of the interlayerdielectric (ILD) upon which the M5 stack is deposited. It is to be notedthat MOCVD deposition is typically very conformal, whereby the thicknessof the dielectric on the sidewalls of the M5 bottom electrodes willtypically be nearly the same to the thickness deposited on the top M5ARC layer.

[0064] Next, in block 78 (FIG. 5), a layer of TiN is deposited over thedielectric layer deposited in block 74, for use as the top electrode ofthe MIM capacitor structure. Deposition may occur using varioustechniques, including both PVD and CVD techniques, e.g., via reactivesputtering at about 12 kW and about 200° C., using a titanium sputtertarget with a purity of about 99.995%, and with wafer bias of about 100Watts used to achieve a film resistivity of about 80 μΩcm. The depositedthickness of the TiN film may vary as discussed above; however, in theillustrated embodiment, a thickness of about 3000 angstroms may be used.

[0065] As shown in FIG. 6D, the conductive material deposition performedin block 78 (FIG. 5) results in the deposition of a TiN layer 116,oriented over the dielectric layer 112, thus resulting in a profile thatcoats the top of each leg and sidewall of the capacitive structure, aswell as on top of the interlayer dielectric (ILD) upon which the M5stack is deposited, but separated therefrom by the dielectric layer 112.

[0066] Next, in block 80 (FIG. 5), the MIM capacitor structure isdefined by photolithography, i.e., the dielectric and TiN layers arepatterned to form the top electrode and insulator layers for thecapacitor, as well as the sidewall spacers discussed above. Typically,the dielectric and TiN layers are patterned using the same photoresistmask. As such, from a processing standpoint, fabrication of a MIMcapacitor structure in the herein-described process only adds onepatterning step to the conventional integrated circuit fabricationprocess.

[0067] As shown in FIG. 6E, by patterning the dielectric layer 112 andTiN layer 116, a top electrode 118 and insulator layer 120 are formedfor the MIM capacitor structure, with the insulator layer 120 interposedbetween the top electrode 118 and the previously-formed bottom electrode108. Moreover, for bonding pad 110, layers 112 and 116 are removed viathe patterning operation to expose the surface of TiN layer 106.

[0068] In addition, in the illustrated embodiment, it is desirable tooversize the bottom electrode 108 relative to the top electrode 118 andinsulator layer 120 of the MIM capacitor structure, which sets theallowable misalignment between the layers of the device, i.e., the topand bottom electrodes. Therefore, the pattern for the TiN/dielectricetch is typically configured to expose a perimeter of about 1 μm aroundthe top surface of bottom electrode 108.

[0069] Also, the patterning performed in block 80 (FIG. 5) also resultsin formation of the sidewall spacers within the channels of the MIMcapacitor structure. In particular, FIG. 6E illustrates sidewall spacers122, having an insulator layer 124 that is interposed between thesidewalls 114 of the bottom electrode 108 and a conductive layer 126. Ofnote, the dielectric layer 112 is etched anisotropically to form theplanar capacitor dielectric 128, and as a result, the conductive layer126 in each sidewall spacer 122 is physically separated from the topelectrode 118.

[0070] One manner of implementing the etch of the dielectric and TiNlayers referenced in block 80 of FIG. 5 is illustrated in greater detailin FIG. 7, which utilizes a multi-rate etching process to etch bothlayers, while avoiding exposure of the aluminum in the M5 layer to theetching chemistry. In this implementation, a BCl₃/Cl₂ etching chemistryis used, and the etch is controlled to stop in the TiN ARC film thatcoats the M5 layer and forms the bottom electrode. As such, in thiscontext the TiN ARC film acts as an etch stop layer for the topelectrode/insulator layer etch.

[0071] Specifically, in block 80A of FIG. 7, conventional photoresistdeposition, exposure and development is utilized to pattern anappropriate photoresist mask for patterning the top electrode andunderlying insulator layer for the MIM capacitor structure. Next, inblocks 80B, 80C and 80D, a three step anisotropic etch is performedthrough the photoresist mask, using an etching chemistry of BCl₃/Cl₂.Other selective or non selective etching chemistries, including BCl₃,Cl₂, CHF₃, SF₆ or combinations thereof, may be used in the alternative.Also, as shown in block 80E, once the anisotropic etch is performed, thephotoresist mask is removed in a manner well known in the art.

[0072] In this multi-step of the anisotropic etch, a first, fasteretching rate of about 300-400 nm/minute is obtained, by performing theetch with a total flow of about 100-200 sccms, a pressure of about 10mTorr-20 mTorr, a source power of about 350-700 Watts, and a bias powerof about 150-230 Watts. Then, the etching rate is lowered to a second,slower etching rate of about 50-100 nm/min, by modifying the total flowto about 100-150 sccms, the pressure to about 8-10 mTorr, the sourcepower to about 200-500 Watts, and the bias power to about 160-180 Watts.

[0073] In various embodiments of the invention, switching from thefaster rate to the slower rate may occur either at a predetermined setpoint or after a predetermined exposure time. For example, reaching theinterface between the TiN and insulator layers may sufficiently alterthe plasma composition in the etching chamber to define a set point thatcan be used to trigger the slow down in the etching rate, or empiricalanalysis can be used to select an appropriate time delay beforetriggering the slow down for a particular MIM capacitor design.Likewise, for termination of the etching process, a set point associatedwith exposure of the TiN ARC film, or an empirically-derived time delay,may be used.

[0074] In the illustrated embodiment, a three step etching process isperformed. The first step is performed at the faster rate until theetching process reaches a point proximate the interface between the TiNand dielectric layers (e.g., within about 30% of the TiN layer to theinterface), then the etching process variables are altered as describedabove to perform a slower etch until the etching process reaches a pointproximate the etch stop layer, here the TiN ARC deposited on the bottomelectrode. In the illustrated embodiment, for example, the first stepcomprises a timed etch that is used to etch through about 70% of the TiNlayer, leaving about 30% of the TiN layer remaining to the interfacewith the dielectric layer. It will be appreciated, however, that inother embodiments the switch from the faster rate to the slower rate canoccur upon or after reaching the interface between the TiN and insulatorlayers.

[0075] Upon switching to the slower rate, a controlled etch is performedin a second step until reaching an endpoint associated with theinterface—i.e., an endpoint associated with the detection of the removalof a sufficient quantity of TiN and the exposure of the tantalumpentoxide. The TiN removal can be determined, for example, by opticalemission endpoint detection using a 703 nm filter. It will beappreciated that another wavelength can be used to detect the endpointgiven the chemistries used.

[0076] Once the endpoint is reached, another timed etch is performed ina third step until reaching the point proximate the etch stop layer,e.g., to a point at which etching has occurred into the etch stop layera distance of about 0 to 250 angstroms. The time of the last timed etchmay be calculated, for example, from the elapsed time from the start ofthe low rate etch until the endpoint is reached, e.g., by selecting atime that is about 30% of this elapsed time.

[0077] It will also be appreciated that, in the context of themulti-rate etching process, different materials may be used as an etchstop layer over the top electrode, including, for example, anyconductive film that is thin enough to absorb and reduce the reflectanceof the exposure wavelength (whether I-line, g-line or DUV), e.g., Ti,Ta, W, Mo, and their silicides. Any other material that preventsexposure of aluminum in the M5 layer to chlorine etching chemistry, andthat is suitable for use in the bottom electrode of the MIM capacitorstructure, may be used in the alternative.

[0078] By utilizing a multi-rate etching process, exposure of theelectrode to chlorine etching chemistries is avoided. One principaladvantage is thus the prevention of corrosion to the lower electrode bychlorine containing compounds. However, it will be appreciated thatother patterning and etching processes may be used in the alternative inother applications.

[0079] Returning to FIG. 5, subsequent to patterning the MIM capacitorstructure, an interlayer dielectric (ILD) layer is deposited in block82. For example, a high density plasma chemical vapor deposition(HDP-CVD) may be used to gap fill the M5 pattern with a dielectricmaterial (e.g., SiO2). Other dielectric deposition techniques may alsobe used. One desirable method, for example, adds a final coat oftetra-ethyl-ortho-silicate (TEOS)-based oxide, which produces aTEOS-based film that typically has a higher deposition rate than theHDP-CVD process, and is thus more economical. Also, such materialstypically strengthen the interconnect structure to better withstand theforces of wire bonding to the bond pads. It may also be desirable tomaintain the wafer temperature during the HDP-CVD process to about400±10° C. to reduce mechanical stress.

[0080] Next, in block 84 (FIG. 5), the ILD layer is planarized usingchemical mechanical polishing (CMP), and in block 86 (FIG. 5), the ILDlayer is patterned to form the M5 vias (V5), using conventionalphotolithography and etch techniques. Vias are typically provided tointerconnect bonding pads, as well as the top electrode of the MIMcapacitor structure, with the M6 layer. Thus, as shown in FIG. 6F,subsequent to deposition, planarization and patterning in blocks 82-86(FIG. 5), an ILD layer 132 is formed, including vias 134 and 136 thatrespectively interconnect M6 with the top electrode 118 and bonding pad110.

[0081] As discussed above, various arrays, sizes and spacings of viasmay be used to interconnect the top electrode of a MIM capacitorstructure to the next conductive layer in an integrated circuit. In thealternative, the top electrode could be coupled to an intermediateconductive path, and routed to either of M5 or M6 therefrom.

[0082] Next, in block 88 (FIG. 5), the vias are filled, e.g., bydepositing tungsten plugs in the vias through the deposition of a Ti/TiNbilayer using PVD or CVD, deposition of tungsten using CVD and CMPplanarization. In the alternative, other conductive materials may beused to fill the vias, e.g., aluminum, copper, or alloys thereof.

[0083] Next, in block 90 (FIG. 5), the M6 layer is deposited andpatterned, using conventional deposition and photolithographytechniques. For example, an Al—Cu/TiN stack may be deposited for the M6layer. Thus, as shown in FIG. 6G, subsequent to deposition andpatterning of the plugs and M6 layer in blocks 88-90 (FIG. 5), plugs 138and 140 are formed in vias 134 and 136 to respectively interconnect anM6 layer 142 with the top electrode 118 and bonding pad 110.

[0084] Subsequent to deposition and patterning of M6, conventionalfabrication steps are performed to complete the integrated circuit, asshown in block 92 of FIG. 5. Various operations may be performed, e.g.,PSG/nitride passivation of the M6 level (at about 500 and about 600 nm,respectively) prior to bond pad mask and etch, and an H₂/N₂ alloytreatment at about 420° C. for about 30 minutes may be performed beforeelectrical testing.

[0085] As a result of the aforementioned process and design, MIMcapacitor structures having capacitance densities at or above 23 fF/μm²can be obtained, thereby offering a substantial improvement overconventional designs, where capacitance densities exceeding 1 fF/μm²(more than an order of magnitude lower) are difficult to achieve.Moreover, it has been found that appropriate leakage current densitycharacteristics, as well as appropriate temperature and voltagelinearity characteristics, can be obtained, while using a fabricationprocess that is compatible with other conventional integrated circuitfabrication processes, and that typically adds only one additionalpatterning step to the process. Furthermore, it is believed that throughdecreasing the surface roughness of the top and/or bottom electrodes(e.g., through the aforementioned annealing and ammonia plasma treatmentoperations), superior capacitance characteristics may be obtained due toimproved characteristics in the insulator layer of the MIM capacitorstructure.

[0086] Various modifications may be made to the illustrated embodimentswithout departing from the spirit and scope of the invention. Forexample, it may be desirable in some applications to deposit TiN orother conductive materials on the sidewalls of the Al—Cu portion of thebottom electrode. Moreover, it may be desirable to pattern the sidewallspacers separately from the top electrode and insulator layer of the MIMcapacitor structure, which would permit, among other benefits, theability to remove the sidewall spacers from non-essential areas, e.g.,in other areas of the M5 layer (e.g., bonding pad 110 shown in FIG. 6G).It may also be desirable to deposit the materials in the sidewallspacers in separate steps, which would permit, among other benefits,different materials, dimensions and layouts to be used for the sidewallspacers.

[0087] Additional modifications will become apparent to one of ordinaryskill in the art. Therefore, the invention lies in the claimshereinafter appended.

WORKING EXAMPLES

[0088] Ammonia Plasma Treatment

[0089] As discussed above, an ammonia plasma treatment may be introducedto prevent oxidation of a TiN lower electrode after M5 deposition. Theprocess described above was tested by processing bare silicon 200-mmtest wafers with different treatment times. A thin silicon nitride filmwas measured after the ammonia treatment. FIG. 8 illustrates theresulting silicon nitride growth on the test wafers.

[0090] The data was taken from a 49-point measurement with a 3 mm edgeexclusion measured by an Optiprobe model 5240, a tool available fromTherma-wave Corporation that uses spectral ellipsometry and fine anglereflectometry to measure stacks of thin transparent films. The 180second treatment time was noted as providing an acceptable compromisebetween processing time and the uniformity of silicon nitride.

[0091] Ammonia plasma treatment was also found to alter voltagelinearity. For test samples constructed using the aforementionedprocess, when varying the voltage from −5 to +5 V, the following resultswere obtained: NH₃ treatment VC1 (ppm/V) VC2 (ppb/V²) No 827 27 Yes 69240

[0092] The temperature coefficient, however, was not found to besignificantly affected by ammonia plasma treatment, e.g., when thetemperature was varied over a range of −50 to 150° C.

[0093] Sidewall Height

[0094] As discussed above, the thickness of the M5 layer, and thus theheight of the resulting sidewall along each leg of the bottom electrode,affects the lateral capacitance effects provided by the sidewallspacers. Twenty five test wafers were fabricated with odd numberedwafers having an M5 layer thickness of about 1 μm, and the even numberedwafers having an M5 layer thickness of about 2 μm, with all otherprocessing variables and dimensions being the same. The resultingcapacitance densities observed are illustrated in FIG. 9, and it can beseen that an improvement of about 5 fF/μm² was obtained due to thedoubling of the thickness of the M5 layer.

What is claimed is:
 1. A method of fabricating a metal-insulator-metal(MIM) capacitor structure in an integrated circuit, the methodcomprising: (a) fabricating first and second legs of MIM capacitorstructure in an integrated circuit, the first and second legs extendinggenerally parallel to one another and defining a channel therebetween,each leg including top and bottom electrodes, an insulator layerinterposed between the top and bottom electrodes, and a sidewall thatfaces the channel; and (b) fabricating a sidewall spacer extending alongthe channel, the sidewall spacer including a conductive layer and adielectric layer interposed between the conductive layer and thesidewall of the first leg, wherein the conductive layer of the sidewallspacer is physically separated from the top electrode.
 2. The method ofclaim 1, wherein fabricating the first and second legs includesfabricating the bottom electrode for the first leg by depositingtitanium nitride.
 3. The method of claim 2, wherein fabricating thebottom electrode for the first leg includes: (a) fabricating aninterconnect layer upon which the titanium nitride is deposited; and (b)patterning the interconnect layer and titanium nitride to define thebottom electrode.
 4. The method of claim 3, wherein fabricating thebottom electrode for the first leg further comprises ammonia plasmatreating a surface of the titanium nitride to improve the surfacebarrier characteristic to oxygen.
 5. The method of claim 1, whereinfabricating the first and second legs includes fabricating the insulatorlayer for the first leg, including depositing high dielectric constantmaterial over the bottom electrode of the first leg.
 6. The method ofclaim 5, further comprising annealing the bottom electrode for the firstleg prior to fabricating the insulator layer for the first leg.
 7. Themethod of claim 6, wherein fabricating the sidewall spacer comprisesdepositing high dielectric constant material over the sidewall of thefirst leg.
 8. The method of claim 7, wherein depositing the highdielectric constant material over the bottom electrode of the first leg,and depositing the high dielectric constant material over the sidewallof the first leg, are performed concurrently.
 9. The method of claim 8,wherein the high dielectric constant material deposited over the bottomelectrode and sidewall of the first leg comprises tantalum pentoxide.10. The method of claim 8, wherein fabricating the first and second legsfurther includes fabricating the top electrode for the first leg bydepositing a conductive material over the insulator layer of the firstleg, and wherein fabricating the sidewall spacer comprises fabricatingthe conductive layer for the sidewall spacer by depositing a conductivematerial over the dielectric layer for the sidewall spacer concurrentlywith depositing the conductive material over the insulator layer of thefirst leg.
 11. The method of claim 10, wherein fabricating the first andsecond legs further includes patterning the top electrode and insulatorlayers of the first leg, and wherein fabricating the sidewall spacerincludes physically separating a portion of the conductive layer in thechannel from the top electrode of the first leg.
 12. The method of claim11, wherein patterning the top electrode and insulator layers of thefirst leg, and physically separating the portion of the conductive layerin the channel are concurrently performed via an anisotropic etchingoperation.
 13. The method of claim 12, wherein the anisotropic etchingoperation includes: (a) patterning a resist layer that covers the firstleg to define the top electrode of the first leg; (b) etching throughthe resist layer at a first rate until reaching a first point proximatean interface between the top electrode the insulator layer of the firstleg; and (c) etching through the resist layer at a second rate that isslower than the first rate until reaching a second point proximate thebottom electrode of the first leg.
 14. The method of claim 13, whereinthe bottom electrode includes an etch stop layer, wherein etchingthrough the resist layer at the second rate is performed until reachinga second point proximate the etch stop layer.
 15. The method of claim 7,wherein depositing the high dielectric constant material over the bottomelectrode of the first leg, and depositing the high dielectric constantmaterial over the sidewall of the first leg, are performed using metalorganic chemical vapor deposition (MOCVD).
 16. The method of claim 1,wherein the MIM capacitor structure includes a serpentine patternincluding a plurality of legs arranged in a generally parallelrelationship.
 17. The method of claim 1, wherein the serpentine patterncomprises a positive serpentine pattern.
 18. The method of claim 1,wherein the serpentine pattern comprises a negative serpentine pattern.19. The method of claim 18, wherein the serpentine pattern additionallycomprises a positive serpentine pattern, wherein the positive andnegative serpentine patterns are interleaved.
 20. Ametal-insulator-metal (MIM) capacitor structure for use in an integratedcircuit, the MIM capacitor structure comprising: (a) first and secondlegs extending generally parallel to one another and defining a channeltherebetween, each leg including top and bottom electrodes, an insulatorlayer interposed between the top and bottom electrodes, and a sidewallthat faces the channel; and (b) a sidewall spacer extending along thechannel, the sidewall spacer including a conductive layer and adielectric insulator layer interposed between the conductive layer andthe sidewall of the first leg, wherein the conductive layer of thesidewall spacer is physically separated from the top electrode.
 21. TheMIM capacitor structure of claim 20, wherein the bottom electrode forthe first leg comprises titanium nitride.
 22. The MIM capacitorstructure of claim 21, wherein the bottom electrode for the first legfurther includes an interconnect layer upon which the titanium nitrideis deposited.
 23. The MIM capacitor structure of claim 22, wherein thetitanium nitride includes an ammonia plasma treated surface.
 24. The MIMcapacitor structure of claim 21, wherein the insulator layer for thefirst leg, and the dielectric layer in the sidewall spacer, eachcomprise a high dielectric constant material.
 25. The MIM capacitorstructure of claim 24, wherein the high dielectric constant material inthe insulator layer for the first leg and the dielectric layer in thesidewall spacer is tantalum pentoxide.
 26. The MIM capacitor structureof claim 24, wherein the top electrode for the first leg includestitanium nitride.
 27. The MIM capacitor structure of claim 20, whereinthe first and second legs are defined within a serpentine pattern. 28.The MIM capacitor structure of claim 20, wherein the serpentine patterncomprises at least one of a positive serpentine pattern and a negativeserpentine pattern.
 29. The MIM capacitor structure of claim 28, whereinthe serpentine pattern comprises a positive serpentine patterninterleaved with a negative serpentine pattern.
 30. A method offabricating a metal-insulator-metal (MIM) capacitor structure in anintegrated circuit, the method comprising: (a) forming first and secondbottom electrodes in an integrated circuit, the first and secondelectrodes extending generally parallel to one another and defining achannel therebetween; (b) depositing an insulator layer over the firstand second bottom electrodes and in the channel; (c) depositing aconductive layer over the insulator layer; and (d) etching the depositedconductive and insulator layers to define first and second topelectrodes opposing the first and second bottom electrodes, and tophysically separate a portion of the conductive layer in the channel.31. The method of claim 30, wherein forming the first and second bottomelectrodes comprises: (a) forming an interconnect layer in theintegrated circuit; (b) depositing an anti-reflective coating (ARC)layer over the interconnect layer; and (c) concurrently patterning theinterconnect and ARC layers to form the first and second bottomelectrodes.
 32. The method of claim 31, wherein the interconnect layercomprises aluminum, copper or a combination thereof, and wherein the ARClayer comprises titanium nitride.
 33. The method of claim 32, whereindepositing the insulator layer over the first and second bottomelectrodes and in the channel comprises depositing tantalum pentoxide.34. The method of claim 33, further comprising ammonia plasma treatingthe ARC layer prior to depositing the insulator layer.
 35. The method ofclaim 34, further comprising annealing the first and second bottomelectrodes prior to depositing the insulator layer.
 36. The method ofclaim 30, wherein etching the deposited conductive and insulator layerscomprises etching the deposited conductive and insulator layersanisotropically.
 37. The method of claim 36, wherein etching thedeposited conductive and insulator layers includes: (a) patterning aresist layer; (b) etching through the resist layer at a first rate untilreaching a first point proximate an interface between the conductive andinsulator layers; and (c) etching through the resist layer at a secondrate that is slower than the first rate until reaching a second pointproximate the first and second bottom electrodes.
 38. The method ofclaim 37, wherein through the resist layer at the first rate includesetching at the first rate for a first period of time, and whereinetching through the resist layer at the second rate includes: (a)etching at the second rate until detecting an endpoint associated withthe interface between the conductive and insulator layers; and (b)thereafter etching at the second rate for a second period of time.
 39. Amethod of fabricating a metal-insulator-metal (MIM) capacitor structurein an integrated circuit, the method comprising ammonia plasma treatinga surface of a bottom electrode of the MIM capacitor structure prior todepositing an insulator layer over the bottom electrode to improve thesurface barrier characteristic to oxygen.
 40. The method of claim 39,wherein the bottom electrode comprises titanium nitride disposed at thesurface of the bottom electrode.
 41. The method of claim 40, wherein theinsulator layer comprises tantalum pentoxide.
 42. The method of claim40, wherein ammonia plasma treating comprises bombarding the titaniumnitride surface with nitrogen ions to inhibit oxidation of the titaniumnitride surface.
 43. The method of claim 40, wherein ammonia plasmatreating is performed in a plasma enhanced chemical vapor depositiontool.
 44. The method of claim 43, wherein ammonia plasma treating isperformed in an atmosphere comprising ammonia and an inert gas.
 45. Themethod of claim 44, wherein ammonia plasma treating is performed in anatmosphere having a pressure of about 10 milliTorr to about 10 Torr anda bottom electrode temperature of about 300 to about 500° C.
 46. Themethod of claim 43, wherein ammonia plasma treating includes applying RFpower including up to about 50% low frequency RF power.
 47. Ametal-insulator-metal (MIM) capacitor structure for use in an integratedcircuit, the MIM capacitor structure comprising: (a) top and bottomelectrodes, wherein the bottom electrode includes an ammonia plasmatreated surface; and (b) an insulator layer interposed between the topelectrode and the ammonia plasma treated surface of the bottomelectrode.
 48. The MIM capacitor structure of claim 47, wherein theammonia plasma treated surface comprises titanium nitride.
 49. The MIMcapacitor structure of claim 48, wherein the insulator layer comprisestantalum pentoxide.
 50. The MIM capacitor structure of claim 48, whereinthe ammonia plasma treated surface is substantially free of titaniumoxide as a result of bombardment of the ammonia plasma treated surfacewith nitrogen ions.
 51. A method of fabricating a metal-insulator-metal(MIM) capacitor structure in an integrated circuit, the methodcomprising: (a) patterning a resist layer that covers a MIM capacitorstructure to define a top electrode, the MIM capacitor structureincluding an etch stop layer, a dielectric layer overlaying the etchstop layer, and a conductive layer overlaying the dielectric layer; (b)etching the M capacitor structure through the resist layer at a firstrate until reaching a first point proximate an interface between theconductive and dielectric layers; and (c) etching the MIM capacitorstructure through the resist layer at a second rate that is slower thanthe first rate until reaching a second point proximate the etch stoplayer.
 52. The method of claim 51, wherein the conductive layer and theetch stop layer each comprise titanium nitride.
 53. The method of claim52, wherein the dielectric layer comprises tantalum pentoxide.
 54. Themethod of claim 51, wherein the etch stop layer is disposed on a bottomelectrode defined for the MIM capacitor structure.
 55. The method ofclaim 54, wherein etching the MIM capacitor structure at the first andsecond rates is performed using etching chemistry that includes at leastone chlorine containing compound, wherein the bottom electrode furthercomprises aluminum, and wherein the etch stop layer is configured toprevent exposure of the aluminum in the bottom electrode to the etchingchemistry.
 56. The method of claim 54, wherein patterning the resistlayer includes defining a pattern in the resist layer viaphotolithography, wherein the etch stop layer is further configured asan anti-reflective coating for the bottom electrode to inhibitreflections when defining the pattern in the resist layer.
 57. Themethod of claim 54, wherein the conductive layer comprises about 300 nmof titanium nitride, wherein the etch stop layer comprises about 30 nmof titanium nitride, wherein the first rate comprises about 300 to about400 nm/minute, and wherein the second rate comprises about 50 to about100 nm/minute.
 58. The method of claim 54, wherein the bottom electrodecomprises first and second legs extending generally parallel to oneanother and defining a channel therebetween, each leg including asidewall that faces the channel, wherein the dielectric layer overlaysthe sidewall of each leg of the bottom electrode, and wherein theconductive layer overlays the dielectric layer that overlays thesidewall of each leg of the bottom electrode, and wherein etching at thefirst and second rates each comprise anisotropically etching such thatsubsequent to etching at the first and second rates a sidewall spacerextends along the channel, the sidewall spacer comprising that portionof the conductive layer and the dielectric layer that overlay thesidewall subsequent to etching at the first and second rates.
 59. Themethod of claim 51, wherein etching the MIM capacitor structure throughthe resist layer at the first rate includes etching the MIM capacitorstructure at the first rate for a first period of time, and whereinetching the MIM capacitor structure through the resist layer at thesecond rate includes: (a) etching the MIM capacitor structure at thesecond rate until detecting an endpoint associated with the interfacebetween the conductive and dielectric layers; and (b) thereafter etchingthe MIM capacitor structure at the second rate for a second period oftime.
 60. The method of claim 59, wherein the first period of time isempirically selected to etch about 70% of the conductive layer.
 61. Themethod of claim 59, further comprising: (a) tracking a third period oftime until detecting the endpoint; and (b) calculating the second periodof time from the third period of time.
 62. The method of claim 61,wherein calculating the second period of time includes selecting thesecond period of time to be about 30% of the third period of time.